The subject matter disclosed herein relates to a system and method for dynamically selecting circuit elements. More particularly, the subject matter disclosed herein relates to a system and method for dynamically selecting circuit elements to improve linearity of a low-noise, low-power delta-sigma (ΔΣ) digital-to-analog converter (DAC).
During digital-to-analog (D/A) conversion, a thermometer code is generated that corresponds to an input digital sample. The thermometer code then is used to select a number of DAC elements that scale the input digital sample in the analog domain. For a D/A conversion process to be linear, the DAC elements are assumed to all be identical. In reality, however, mismatches among DAC elements exist and conventional DAC element-selection schemes produce code-dependent errors that are manifested as a conversion distortion.
A conventional Data Weight Average (DWA) algorithm is typically used to whiten the code-dependent errors as well as provide a first-order mismatch noise shaping, thereby moving most of the resulting white-noise power beyond the signal band. (See, for example, R. T. Baird, and T. S. Fiez, “Improved ΔΣ DAC linearity using data weighted averaging,” Proc. IEEE International Symposium on Circuits and Systems, May 1995, Vol. 1, pp. 13-16). The first-order mismatch noise shaping of this algorithm is a result of the requirement that the number of selected DAC elements linearly scale the input digital sample code. Accordingly, to implement this algorithm with first order mismatch noise shaping, a signed input code set must first be linearly mapped to a non-negative code set because a code sign change cannot be linearly handled by a conventional DWA element rotation algorithm.
Consider, for example, an input signed 2-bit digital code set [−3, −1, +1, +3] that is to be converted to the corresponding analog output values of [−3V, −1V, +1V, +3V]. FIG. 1 depicts an exemplary functional block diagram of a conventional single-ended DAC configuration 100 that implements a conventional DWA algorithm. The signed code set is initially converted into a non-negative code, such as,[−3, −1, +1, +3]→[0, 1, 2, 3].
At 101 in FIG. 1, the signed input 2-bit digital code set [−3, −1, +1, +3] has already been converted into the non-negative code [0, 1, 2, 3] in a well-known manner and is not shown. At 102, a conventional DWA algorithm is implemented to provide dynamic element matching (DEM). DAC 103 (of which only one DAC element of a plurality of DAC element are shown) is selected by the DEM 102 and the non-negative code is converted as[0, 1, 2, 3]→[6Vr/R, 4Vr/R, 2Vr/R, 0],in which Vr is a reference voltage, and Vr/R is a reference current corresponding to reference voltage Vr. That is, DAC element 103 outputs currents [6Vr/R, 4Vr/R, 2Vr/R, 0] respectively corresponding to the non-negative code [0, 1, 2, 3] at 104. The non-negative code set is re-centered by adding a DC offset that is provided by current source 105. At 107, filter 106 outputs re-centered code [−3Vr, −Vr, +Vr, +3Vr].
Although a conventional DWA algorithm reduces the in-band mismatch noise by a first-order noise shaping, adding a DC offset, such as shown in FIG. 1, injects unnecessary noise into the DAC output. Moreover, extra power is wasted because the circuitry performing the DC offset is not part of the DAC output signal.
For a high-performance DAC system, two identical DACs are conventionally used to form a pseudo-differential DAC. FIG. 2 depicts an exemplary functional block diagram for a conventional pseudo-differential DAC configuration 200. At 201 in FIG. 2, a signed input 2-bit digital code set [−3,−1,+1,+3] has already been converted into two non-negative code sets [0, 1, 2, 3] and [3, 2, 1, 0] in a well-known manner and is not shown. A conventional DWA algorithm is implemented twice at 202a and 202b to provide dynamic element matching (DEM). DACs 203a and 203b (of which only one DAC element of a plurality of DAC elements is shown in each case) respectively provide DAC currents [3Vr/R, 2Vr/R, Vr/R, 0] and [0, Vr/R, 2Vr/R, 3Vr/R] at 204a and 204b. The two non-negative code sets are respectively re-centered by adding DC offsets at 205a and 205b. At 207, differential filter 206 outputs the re-centered code [−3Vr, −Vr, +Vr, +3Vr] as a pseudo-differential DAC output.
A conventional pseudo-differential DAC configuration, similar to the conventional single-ended DAC configuration of FIG. 1, is not power or area efficient, and the offset currents degrade the signal-path noise performance. Additionally, the conventional circuitry providing DC offsets inject additional thermal noise into the signal path.